monitor.c File Reference


Detailed Description

Copyright (C) 1999 by Denis Chertykov (denisc@overta.ru) STK200 communication added by Tor Ringstad (torhr@pvv.ntnaddr.no).

You can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version.

This program works with the connection scheme used in Atmels "STK200 Starter Kit". The connection allows to program the AVR with Uros Platise `uisp' in `-dstk200' mode.

Bugs: For me this work only if Parallell port in EPP mode. May be ECP mode also work?

2002 June Jörgen Birkler (birkler@yahoo.com)

2003 April Jörgen Birkler (birkler@yahoo.com)

2003 November Jörgen Birkler (birkler@yahoo.com)

Defines

Functions

Variables


Define Documentation

#define MONITOR_INTERRUPT
 

Todo:
More hardware configurations

jbirkler:Add Timer1 and Timer2 to supported interrupts

 
#define SPI_SLAVE_INIT  ) 
 

Enable for slave MISO is output, everything else is input with pull-up enabled

Author:
Jorgen Birkler (birkler@yahoo.com)

#define AVR_MONITOR_IS_RX_SYNC val   ) 
 

Sync host to target communication with a trailing 10 ones followed by 4 zeros.

Author:
Jorgen Birkler (birkler@yahoo.com)
00111111111100xxxxxxxx


Function Documentation

void monitor void   ) 
 

int16_t SPI_Slave_Transfer uint8_t  tx_byte  )  [static]
 

Slave transmit Wait until the previous tranfer is complete and writes to the data register

Author:
Jorgen Birkler (birkler@yahoo.com)
Its seems that the SPIF bit in SPSR is set after 8 bits have been shifted into the shift register not when SS goes high. The datasheet doesn't explicitly say but when reading the text you can get the impression that SS low-high triggers the SPIF bit, this is not so. The hardware seems also to be very confused if there is not exactly 8 bits. 7 bits = nothing, 9 bits = garbage.

By enabling clock phase CPHA (after testing I found that this works in mode 1 but not in mode 0) it is possible to piggy pack a bit from the host to the target (remember that MOSI is controlling SS; MOSI cannot be used) by letting the SPI_SCK be either 1 or 0 when SS goes high.

Bytes in the piggy back bit is synced so that the target can determine when it received a complete byte, see AVR_MONITOR_IS_RX_SYNC.

Parameters:
tx_byte Byte to send
Return values:
-1 no byte recieved
0..255 byte recieved

void Monitor_SendChar uint8_t  data  ) 
 

High level routine for sending one byte of data. Blocks until the host is ready to receive.

uint8_t Monitor_ReceiveByte void   )  [static]
 

High level routine for receiving one byte of data. Blocks until the host is ready to send.

void MONITOR_INTERRUPT void   ) 
 


Copyright 2002 Jörgen Birkler. For accelR8 Accelerometer on Mon Jan 19 21:43:19 2004 by Doxygen 1.3.5.